FIG. 1 is a block diagram of a conventional ΔΣ fractional-N PLL. The purpose of the system is to generate an output signal of frequency (N+α)fref where N is a positive integer, α is a constant fractional value between 0 and 1, and fref is the frequency of a reference oscillator. The system consists of a phase-frequency detector (PFD) and a charge pump 100, a loop filter 102, a voltage controlled oscillator (VCO) 104, a multi-modulus divider 106, and a digital ΔΣ modulator 108. The divider output, vdiv(t), is a two-level signal in which the nth and (n+1)th rising edges are separated by N+y[n] periods of the VCO output, for n=1, 2, 3, . . . , where y[n] is a sequence of integers generated by the ΔΣ modulator 108. As indicated in FIG. 1B for the case where the PLL, is locked, if the nth rising edge of the reference signal, vref(t), occurs before that of vdiv(t), the charge pump 100 generates a positive current pulse of magnitude ICP with a duration equal to the time difference between the two edges. This increases the VCO control voltage, vctrl(t), thereby increasing the VCO output frequency. Alternatively, if the nth rising edge of vref(t), occurs after that of vdiv(t), the situation is similar except the polarity of the current pulse is negative, which decreases the VCO frequency.
If y[n] could be set directly to the desired fractional value, α, then the output frequency of the PLL would settle to (N+α)fref. Unfortunately, y[n] is is restricted to integer values because the divider 106 is only able to count integer VCO cycles. To circumvent this limitation, the ΔΣ modulator 108 generates a sequence of integer values that average to α. The sequence can be written as y[n]=a+eΔΣ[n], where eΔΣ[n] is zero-mean quantization noise. Thus, the PLL output frequency settles to (N+α)fref as desired, although a price is paid in terms of added phase noise resulting from the quantization noise.
As shown in M. H. Perrott, M. D. Trott, C. G. Sodini, “A Modeling Approach for D-S Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis,” IEEE Journal of Solid State Circuits. Vol. 37, No. 8, pp. 1028-38, August 2002, in terms of its effect on the PLL phase noise, the quantization noise can be modeled as a sequence of additive charge samples, Qcp-ΔΣ[n], that get injected into the loop filter once every reference period. Neglecting a constant offset associated with the initial conditions of the loop filter, it can be shown that Qcp-ΔΣ[n] is given by
                                                        Q                              cp                ·                ΔΣ                                      ⁡                          [              n              ]                                =                                    T              VCO                        ⁢                          I              CP                        ⁢                                          ∑                                  k                  =                                      n                    0                                                                    n                  -                  1                                            ⁢                                                e                  ΔΣ                                ⁡                                  [                  k                  ]                                                                    ,                            (        1        )            where TVCO is the period of the VCO output (for a given value of α, TVCO is well-modeled as a constant) and n0<n is an arbitrary initial time index. The PLL has the effect of lowpass filtering Qcp-ΔΣ[n] in the process of converting it to output phase noise.
The ΔΣ modulator 108 quantizes its input in such a way that eΔΣ[n] is spectrally shaped with most of its power concentrated at high frequencies. For example, in a properly dithered second-order ΔΣ modulator, eΔΣ[n] has a power spectral density (PSD) equal to that of discrete-time white noise with variance 1/12 passed through a high pass filter. In the example embodiment that uses a 2nd order delta sigma modulator, the high pass filter has a transfer function (1−z−1)2. It follows from (1) that this causes Qcp-ΔΣ[n] to have a PSD equal to that of discrete-time white noise with variance (TVCOICP)2/12 passed through a highpass filter with transfer function 1−z−1. Hence, the PSD of Qcp-ΔΣ[n] has a zero at DC and rises at 6 dB per octave in frequency until nearly half the reference frequency. Provided the bandwidth of the PLL is very narrow, most of the power in Qcp-ΔΣ[n] is suppressed by the PLL so it has only a small effect on the overall PLL phase noise. However, as the PLL bandwidth is increased, less of the power in Qcp-ΔΣ[n] is suppressed by the PLL, so its contribution to the PLL phase noise becomes more dominant. Thus, there is a fundamental bandwidth versus phase noise tradeoff in conventional ΔΣ fractional-N PLLs.
Phase noise cancelling ΔΣ fractional-N PLLs attempt to circumvent this tradeoff by cancelling the quantization noise prior to the loop filter, thereby eliminating the need for narrow-band filtering by the PLL to suppress the quantization noise. FIG. 2 shows an example, wherein the idea is to add a phase noise cancellation path 200, 202 to a conventional ΔΣ fractional-N PLL. The phase noise cancellation path discrete-time integrates the ΔΣ quantization noise to obtain the digital sequence
                                                        e              cp                        ⁡                          [              n              ]                                =                                    ∑                              k                =                                  n                  0                                                            n                -                1                                      ⁢                                          e                ΔΣ                            ⁡                              [                n                ]                                                    ,                            (        2        )            and converts −ecp[n] via the DAC 202 into a current pulse of duration TDAC and amplitude −ecp[n]TVCOICP/TDAC. To the extent that this can be done accurately, it follows from (1) and (2) that the charge in each DAC pulse cancels the Qcp-ΔΣ[n] portion of the charge in the corresponding charge pump pulse.
In practice, the gain of the DAC 202 is never perfectly matched to that of the signal path through the PFD and charge pump 100, so the cancellation of quantization noise is imperfect. Component mismatches and non-ideal circuit behavior cause both amplitude and transient mismatches between the signals generated by the DAC 202 and the charge pump 100. This can be modeled by considering the actual amount of charge in each DAC pulse to deviate from its ideal value of −ecp[n]TVCOICP by a factor of (1+β), where β is a small constant that represents the cancellation path mismatch. As shown in S. Pamarti, I. Galton, “Phase-noise Cancellation Design Tradeoffs in Delta-Sigma Fractional-N PLLs”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 50. No. 11, pp. 829-838, November 2003, the PSD of the component of the PLL phase noise resulting from imperfect cancellation of the quantization noise is given approximately by
                                                        S                              θ                PLL                                      ⁡                          (                              j2π                ⁢                                                                  ⁢                f                            )                                ⁢                      |                          Δ              ⁢                                                          ⁢              Σ              ⁢                                                          ⁢              only                                      =                              β            2                    ⁢                                    π              2                                      3              ⁢                              f                ref                                              ⁢                                                                  2                ⁢                                  sin                  ⁡                                      (                                                                  π                        ⁢                                                                                                  ⁢                        f                                                                    f                        ref                                                              )                                                                                                    2              ⁢                              (                                  L                  -                  1                                )                                              ⁢                                                                                    A                  θ                                ⁡                                  (                                      j2π                    ⁢                                                                                  ⁢                    f                                    )                                                                    2                    ⁢                      rad            2                    ⁢                      /                    ⁢          Hz                                    (        3        )            where A0 (s) is the lowpass transfer function of the PLL from the phase of the reference oscillator to the phase of the PLL output normalized to unity at s=0, and L is the order of the ΔΣ modulator.
In general, A0(j2πf), has a bandwidth much less than the reference frequency. Given that sin(x)≈x when |x|<<1, it follows from (3) that the integrated phase noise associated with imperfect quantization noise cancellation is approximately proportional to β2/fref2L−1. This indicates how the matching accuracy required for a given level of phase noise cancellation depends on the reference frequency. For example, suppose two phase noise cancelling PLLs have equal bandwidths and ΔΣ modulator orders, but their reference frequencies and DAC gain mismatches are given by fref1 and fref2 and β1 and β2, respectively. To ensure that the portions of their integrated phase noise powers associated with imperfect quantization noise cancellation are equal, it follows that the relation
                                          β            1            2                                f                          ref              ⁢                                                          ⁢              1                                                      2                ⁢                L                            -              1                                      =                              β            2            2                                f                          ref              ⁢                                                          ⁢              2                                                      2                ⁢                L                            -              1                                                          (        4        )            must hold. In particular, if fref2=fref1/2, then β2=β1/2L−1/2. Thus, phase noise cancellation becomes increasingly difficult as the reference frequency is decreased. For example, if the reference frequency of a ΔΣ fractional-N PLL is halved without changing the PLL bandwidth or the cancellation path matching accuracy, then the power of the output phase noise arising from imperfect cancellation increases by 6(L−½) dB where L is the ΔΣ modulation order (usually L=2 or 3). The adaptive calibration method of the invention addresses this problem by adaptively adjusting the DAC gain in one of the preferred embodiments to is minimize |β|.
In addition to the gain mismatch problem described above, another type of mismatch between the charge pump and DAC occurs in practice. Specifically, the charge pump pulses have a fixed amplitude and variable widths, whereas the DAC pulses have a fixed width and variable amplitudes. Unfortunately, this discrepancy is dictated by circuit limitations; as of the time of the invention it has not been practical to generate the timing signals needed to implement width-modulated DAC pulses that have sufficient accuracy. The result of the discrepancy is illustrated in FIG. 3 for the ideal matching case of β=0. The component of vctrl(t) corresponding to quantization noise indeed goes to zero between DAC and charge pump pulses, but the cancellation is imperfect during the DAC and charge pump pulses. Thus, even if |β| is made negligibly small, the quantization noise cancellation is imperfect in practice. Fortunately, the resulting phase noise is typically very small provided TDAC is relatively small and the DAC pulses are timed so as to overlap the charge pump pulses as much as possible. Alternatively, a sampled loop filter configuration can be used to address the problem as described in S. E. Meninger and M. H. Perrott, “A 1 MHz Bandwidth 3.6 GHz 0.18 μm CMOS fractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise,” IEEE Journal of Solid-State Circuits, Vol. 41. No. 4, pp. 966-980, April 2006.
As described above, phase noise cancellation makes it possible to greatly widen the loop bandwidth of a delta-sigma fractional-N PLL without the massive increase in phase noise that would otherwise be caused by the delta-sigma quantization noise. This allows the loop filter to be integrated on-chip, reduces sensitivity to VCO pulling and noise, better attenuates in-band VCO noise, and makes direct digital frequency modulation practical in wireless applications such as GSM and Bluetooth. However, good phase noise cancellation requires good matching of the cancellation and signal paths, and the matching precision required for a given level of performance increases dramatically as the reference frequency is decreased.
Example PLLs with phase noise cancellation based on passive matching have required reference frequencies of 35 MHz, 48 MHz, and 50 MHz to achieve 15 dB, 20 dB, and 29 dB of phase noise cancellation, respectively. See, E. Temporiti, G. Albasini, I. Bietti, R. Castello, M. Colombom “A 700 kHz Bandwidth ΣΔ Fractional Synthesizer with Spurs Compensation and Linearization Techniques for WCDMA Applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1446-54 (September 2004); S. Pamarti, L. Jansson, 1. Galton, “A Wideband 2.4 GHz ΔΣ A Fractional-N PLL with 1 Mb/s In-loop Modulation,” IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 49-62 (January 2004); S. E. Meninger, and M. H. Perrott; and “A 1 MHz Bandwidth 3.6 GHz 0.18 um CMOS Fractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 966-980 (2006). The need for such high reference frequencies represents a major limitation of phase noise cancellation with passive matching in wireless applications.
Adaptive Calibration
In principle, the sign-error LMS algorithm can be used to adaptively adjust the DAC gain to minimize |β|. See, e.g., Ali H. Saved, Fundamentals of Adaptive Filtering, Wiley-Interscience, 2003. Whenever the DAC gain is not ideal, imperfect cancellation of the quantization noise causes the charge pump and DAC pulses to inject an undesired net charge of βQcp-ΔΣ[n]=βTVCOICPecp[n] into the loop filter each reference period. Suppose that a copy of these current pulses were multiplied by the sign of ecp[n], i.e., by
                              sgn          ⁢                                          ⁢                      {                                          e                cp                            ⁡                              [                n                ]                                      }                          =                  {                                                                      1                  ,                                                                                                                        if                      ⁢                                                                                          ⁢                                                                        e                          cp                                                ⁡                                                  [                          n                          ]                                                                                      ≥                    0                                    ,                                                                                                                          -                    1                                    ,                                                                                                                        if                      ⁢                                                                                          ⁢                                                                        e                          cp                                                ⁡                                                  [                          n                          ]                                                                                      <                    0                                    ,                                                                                        (        5        )            and then injected into an integrating lowpass filter (i.e., a lowpass filter with a pole at s=0). In general, sgn{ecp[n]}has zero mean and is uncorrelated with all the noise sources in the PLL other than the quantization noise. Moreover, ecp[n]sgn{ecp[n]}=|ecp[n]|. Therefore, if β>0, the output of the integrating lowpass filter would ramp up over time, and if β<0, it would ramp down over time. If the output of the integrating lowpass filter were used to control the gain of the DAC in a stable negative feedback configuration, then the feedback loop would continuously adjust the DAC gain toward the ideal case of B=0.
In practice, however, creating sufficiently accurate copies of the DAC and charge pump pulses multiplied by ecp[n] is challenging. This problem is circumvented in M. Gupta and B. S. Song, “A 1.8 GHz Spur Cancelled Fractional-N Frequency Synthesizer with LMS Based DAC Gain Calibration,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 12, pp. 2842-851, December 2006 by simply multiplying a buffered copy of vctrl(t) by sgn{ecp[n]} as depicted in FIG. 4A. It can be shown that the resulting system implements an approximate version of the sign-error LMS algorithm described above. Although the feedback loop can be made to work properly, a practical problem arises because of the DC component in vctrl(t). The DC component is necessary because it sets the frequency of the VCO, and the range of values it can take on as a function of the desired output frequency tends to be large. The problem is that the DC component gets multiplied by sgn{ecp[n]} and then fed back through an integrator 402 to control the DAC gain. If the feedback loop bandwidth is not sufficiently small, the resulting modulation of the DAC gain severely degrades the phase noise performance of the PLL. Unfortunately, as demonstrated via simulation results shown in FIG. 4B, the PSD of sgn{ecp[n]}tends to have large spurious tones. See, S. Pamarti, L. Jansson, I. Galton, “A Wideband 2.4 GHz ΔΣ Fractional-N PLL with 1 Mb/s in-loop Modulation,” IEEE Journal of Solid-State Circuits. Vol. 39, No. 1, pp. 49-62, January 2004 and K. Wang, A. Swaminathan, I. Galton, “Spurious tone suppression techniques applied to a wide-bandwidth 2.4 GHz Fractional-N PLL,” IEEE Journal of Solid-State Circuits, vol. 43, no 12, December 2008. The tones arise from the strong non-linearity imposed by the sgn{ }function, even when the ΔΣ modulator's quantization noise is free of spurious tones. The tone frequencies are multiples of αfref, so they decrease with the fractional frequency value, α. Therefore, the LMS feedback loop bandwidth must be made very small to sufficiently attenuate the tones, and this results in very slow adaptive calibration settling. For example, the settling time has been reported in M. Gupta and B. S. Song, “A 1.8 GHz Spur Cancelled Fractional-N Frequency Synthesizer with LMS based DAC Gain Calibration.” IEEE Journal of Solid-State Circuits. Vol. 41, No. 12, pp. 2842-851, December 2006 to be approximately 1 second.